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W631GG6KB
8.2.2
Reset Initialization with Stable Power
The following sequence is required for RESET at no power interruption initialization.
1. Asserted RESET below 0.2 * V DD anytime when reset is needed (all other inputs may be
undefined). RESET needs to be maintained for minimum 100 nS . CKE is pulled ―LOW‖ before
RESET being de-asserted (min. time 10 nS).
2. Follow Power-up Initialization Sequence steps 2 to 11.
3. The Reset sequence is now completed; DDR3 SDRAM is ready for normal operation.
Ta
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
Tj
Tk
CK, CK#
t CKSRX
VDD, VDDQ
RESET#
T = 100 ns
T = 500 μs
CKE
Tmin = 10 ns
t IS
t DLLK
VALID
t XPR
t MRD
t MRD
t MRD
t MOD
t ZQ init
t IS
Command
*1
MRS
MRS
MRS
MRS
ZQCL
*1
VALID
BA
MR2
MR3
MR1
MR0
VALID
t IS
t IS
Note:
ODT
RTT
Static LOW in case Rtt_Nom is enabled at time Tg, Otherwise static HIGH or LOW
TIME BREAK
VALID
DON'T CARE
1.
From time point ―Td‖ until ―Tk‖ NOP or DES commands must be applied between MRS and ZQCL commands.
Figure 2 – Reset Procedure at Power Stable Condition
Publication Release Date: Dec. 09, 2013
Revision A05
- 14 -
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